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CY23FS08
FailsafeTM 2.5V/ 3.3V Zero Delay Buffer
Features
* Internal DCXO for continuous glitch-free operation * Zero input-output propagation delay * 100ps typical output cycle-to-cycle jitter * 110 ps typical Output-output skew * 1 MHz-200 MHz reference input * Supports industry standard input crystals * 200 MHz (commercial), 166 MHz (industrial) outputs * 5V-tolerant inputs * Phase-locked loop (PLL) Bypass Mode * Dual Reference Inputs * 28-pin SSOP * Split 2.5V or 3.3V output power supplies * 3.3V core power supply * Industrial temperature available
Functional Description
The CY23FS08 is a FailSafeTM Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. Continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS08 is that the DCXO is in fact the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal, which will be connected to the DCXO must be chosen to be an integer factor of the frequency of the reference clock. This factor is set by four select lines: S[4:1]. please see Table 1. The CY23FS08 has three split power supplies; one for core, another for Bank A outputs and the third for Bank B outputs. Each output power supply, except VDDC can be connected to either 2.5V or 3.3V. VDDC is the power supply pin for internal circuits and must be connected to 3.3V.
Block Diagram
Pin Configuration
XIN XOUT REFSEL DCXO
REF1 REF2 VSSB CLKB1
4
REF1 REF2 FBK FailsafeTM Block PLL
CLKA[1:4] CLKB[1:4]
CLKB2 S2 S3 VDDB VSSB CLKB3
4
Decoder FAIL# /SAFE S[4:1] 4
CLKB4 VDDB VDDC XIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14
CY23FS08
28 27 26 25 24 23 22 21 20 19 18 17 16 15
REFSEL FBK VSSA CLKA1 CLKA2 S1 S4 VDDA VSSA CLKA3 CLKA4 VDDA FAIL#/SAFE XOUT
28-pin SSOP
Cypress Semiconductor Corporation Document #: 38-07518 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 2, 2006
CY23FS08
Pin Definitions
Pin Number 1,2 4,5,10,11 25,24,19,18 27 23,6,7,22 14 15 16 13 8,12 3,9 17,21 20,26 28 Pin Name REF1,REF2 CLKB[1:4] CLKA[1:4] FBK S[1:4] XIN XOUT FAIL#/SAFE VDDC VDDB VSSB VDDA VSSA REFSEL 5V-tolerant, reference clock Bank B clock outputs.[1, 2] Bank A clock outputs.[1, 2] Feedback input to the PLL.[1, ] Frequency select pins/PLL and DCXO bypass.[3] Reference crystal input. Reference crystal output. Valid reference indicator. A high level indicates a valid reference input. 3.3V power supply for the internal circuitry. 2.5V or 3.3V power supply for Bank B outputs. Ground. 2.5V or 3.3V power supply for Bank A outputs. Ground. Reference select. Selects the active reference clock from either REF1 or REF2. REFSEL = 1, REF1 is selected, REFSEL = 0, REF2 is selected. Description inputs[4] .
Table 1. Configuration Table XTAL (MHz) S[4:1] 0000 1000 1110 0101 1011 0011 1001 1111 1100 0001 0110 1101 0100 1010 0010 0111 8.33 9.50 8.50 8.33 8.33 8.33 8.00 8.00 8.33 8.33 8.33 8.33 8.33 8.33 8.33 30 30 30 30 30 30 25 25 30 30 30 30 30 30 30 16.67 57.00 6.80 25.00 2.78 8.33 32.00 64.00 1.04 4.17 16.67 4.17 12.50 1.39 6.25 60.00 180.00 24.00 90.00 10.00 30.00 100.00 200.00 3.75 15.00 60.00 15.00 45.00 5.00 22.50 Min. Max. REF(MHz) Min. Max. OUT(MHz) Min. 8.33 28.50 1.70 6.25 2.78 8.33 32.00 64.00 2.08 8.33 33.33 16.67 50.00 11.11 50.00 Max. 30.00 90.00 6.00 22.50 10.00 30.00 100.00 200.00 7.50 30.00 120.00 60.00 180.00 40.00 180.00 REF:OUT ratio /2 /2 /4 /4 x1 x1 x1 x1 x2 x2 x2 x4 x4 x8 x8 REF:XTAL ratio Out:XTAL ratio 2 6 4/5 3 1/3 1 4 8 1/8 1/2 2 1/2 3/2 1/6 3/4 1 3 1/5 3/4 1/3 1 4 8 1/4 1 4 2 6 4/3 6
PLL and DCXO Bypass mode
Notes: 1. For normal operation, connect either one of the eight clock outputs to the FBK input. 2. Weak pull-downs on all outputs. 3. Weak pull-ups on these inputs. 4. Weak pull-downs on these inputs.
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CY23FS08
FailSafe Function
The CY23FS08 is targeted at clock distribution applications that could or which currently require continued operation should the main reference clock fail. Existing approaches to this requirement have utilized multiple reference clocks with either internal or external methods for switching between references. The problem with this technique is that it leads to interruptions (or glitches) when transitioning from one reference to another, often requiring complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL, greatly simplifying system design. The CY23FS08 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to reference via the external feedback loop. This is accomplished by utilizing a digitally controlled capacitor array to pull the crystal frequency over an approximate range of 300 ppm from its nominal frequency. In this mode, should the reference frequency fail (i.e., stop or disappear), the DCXO maintains its last setting and a flag signal (FAIL#/SAFE) is set to indicate failure of the reference clock. The CY23FS08 provides four select bits, S1 through S4 to control the reference to crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the DCXO capture range. If the frequency is out of range, a flag will be set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag will be cleared, indicating to the system that the selected reference is valid.
REF OUT F A IL # /S A F E
tF S L
tF S H
Figure 1. Fail#/Safe Timing for Input Reference Failing Catastrophically
t F S L (m a x )
= 2 ( tR E F x n ) + 25ns F REF n= ( in a b o v e e x a m p le ) F XTAL = 4
t F S H ( m in ) =
12(
tR E F x n
)
+
25ns
Figure 2. Fail#/Safe Timing Formula
Table 2. FailSafe Timing Table Parameter tFSL tFSH Description Fail#/Safe Assert Delay Fail#/Safe Deassert Delay Conditions Measured at 80% to 20%, Load = 15 pF Measured at 80% to 20%, Load = 15 pF See Figure 2 Min. Max. See Figure 2 Unit ns ns
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CY23FS08
Reference + 300 ppm Reference Reference - 300 ppm
Reference Off Frequency
Output + 300 ppm Output Output - 300 ppm
Fail#/Safe Volt
tFSH tFSL Time
Figure 3. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range
Failsafe typical frequency settling time
Initial valid Ref1 = 20 MHz +100 ppm, then switching to REF2 = 20 MHz OUTPUT FREQUENCY DELTA (ppm)
150
100
50
0 0 0.45 1.3
SETTLING TIME (ms)
2.5
Figure 4. FailSafe Reference Switching Behavior
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CY23FS08
Figure 5. FailSafe Effective Loop Bandwidth (min)
REF1
REF2
REFSEL 0 ms
0 d eg
-1 8 0 d e g
0 ms 1 .4 m s
Figure 6. Sample Timing of Muxing Between Two Reference Clocks 180C Out of Phase and Resulting Output Phase Offset Typical Settling Time (105 MHz)
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CY23FS08
190 fs/cy 0 0 ms
190 fs/cycle = 0.125 mradian/cycle
1.4 ms
Figure 7. Resulting Output Dphase/Cycle Typical Rate of Change (105 MHz)
D u ty C y c le - t D C V D D /2 V D D /2 t1 t2 S le w R a te - t (S R ) 80% 20% t S R (O ) O u tp u t-O u tp u t S k e w - t S K (O ) V D D /2 t S R (O ) 80% 20% 0V V DD V D D /2 V DD 0V
V D D /2 t S K (O ) P a rt to P a rt S k e w - t S K (P P ) FBK, P a rt 1 FBK, P a rt 2 V D D /2
V D D /2 t S K (P P )
S ta tic P h a s e O ffs e t - t ( ) REF V D D /2
FBK
V D D /2 t ( )
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CY23FS08
XTAL Selection Criteria and Application Example
Choosing the appropriate XTAL will ensure the FailSafe device will be able to span an appropriate frequency of operation. Also, the XTAL parameters will determine the holdover frequency stability. Critical parameters are as follows. Our recommendation is to choose: * Low C0/C1 ratio (240 or less) so that the XTAL has enough range of pullability. * Low temperature frequency variation * Low manufacturing frequency tolerance * Low aging. C0 is the XTAL shunt capacitance (3 pF-7 pF typ.). C1 is the XTAL motional capacitance (10 fF-30 fF typ). The capacitive load as "seen" by the XTAL is across its terminals. It is named Clmin (for minimum value), and Clmax (for maximum value).These are used for calculating the pull range. Please note that the Cl range "center" is approximately 20 pF, but we may not want a XTAL calibrated to that load. This is because the pullability is not linear, as represented in the equation above. Plotting the pullability of the XTAL shows this expected behavior as shown in Figure 8. In this example, specifying a XTAL calibrated to 14 pF load provides a balanced ppm pullability range around the nominal frequency.
Example:[5]
Clmin = (12 pF IC input cap + 0 pF pulling cap+ 6 pF trace cap on board)/2 = 9 pF Clmax = (12 pF IC input cap + 48 pF pulling cap+ 6 pF trace cap on board)/2 = 33 pF Pull Range =(fClmin-fClmax)/fClmin = ((C1)/2)[(1/(C0+Clmin))-(1/(C0+Clmax))] Pull Range in ppm = ((C1)/2)[(1/(C0+Clmin))-(1/(C0+Clmax))] x 106
Pullability Range Vs. Cload
(Normalized to 14pF Cload) 400.00
Delta Freq. from nom
300.00 200.00 100.00 0.00 -100.00 -200.00 -300.00 -400.00 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
Cload (pF)
C0/C1 = 200 C0/C1 = 300 C0/C1 = 400
Figure 8. Frequency vs. Cload Behavior for Example XTAL
Note: 5. The above example shows the maximum range the FailSafe internal capacitor array is capable of (0 to 48.6 pF).Cypress recommends the min./max capacitor array values be programmed to a narrower range such as 6 pF-30 pF, or 7.5 pF-27 pF. This ensures the XTAL operates between series resonance and anti-resonance. Please contact Cypress for choosing these range settings.
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CY23FS08
Table 3. Pullability Range from XTAL with Different C0/C1 Ratio C0/C1 Ratio 200 300 400 Cload(min.) 8.0 8.0 8.0 Cload(max.) 32.0 32.0 32.0 Pullability Range -385 333 -256 222 -192 166 Calculating the capture range involves subtracting error tolerances as follows: Parameter ........................................................ f error (ppm) Manufacturing frequency tolerance ...................................15 Temperature stability ..........................................................30 Aging ................................................................................... 3 Board/trace variation ........................................................... 5 Total ....................................................................................53 Example: Capture Range for XTAL with C0/C1 Ratio of 200 Negative Capture Range= -385 ppm + 53 ppm = -332 ppm Positive Capture Range = 333 ppm - 53 ppm = +280 ppm It is important to note that the XTAL with lower C0/C1 ratio has wider pullability/capture range as compared to the higher C0/C1 ratio. This will help the user in selecting the appropriate XTAL for use in the FailSafe application.
Calculated value of the pullability range for the XTAL with C0/C1 ratio of 200, 300 and 400 are shown in Table 3. For this calculation Cl(min) = 8pF and Cl(max)= 32pF has been used. Using a XTAL that has a nominal frequency specified at load capacitance of 14pF, almost symmetrical pullability range has been obtained. Next, it is important to calculate the pullability range including error tolerances. This would be the capture range of the input reference frequency that the FailSafe device and XTAL combination would reliably span.
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CY23FS08
Absolute Maximum Conditions
Parameter VDD VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Description Supply Voltage Relative to VSS Non Functional Commercial Grade Industrial Grade Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. 2000 36.17 100.6 V-0 1 Condition Min. -0.5 -0.5 -65 0 -40 Max. 4.6 VDD+0.5 +150 70 85 125 Unit V VDC C C C C V C/W C/W
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Recommended Pullable Crystal Specifications[6]
Parameter FNOM CLNOM R1 R3/R1 DL F3SEPLI F3SEPLO C0 C0/C1 C1 Name Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed Comments Parallel resonance, fundamental mode, AT cut Min. 8.00 - - 3 - 300 - - 180 14.4 Typ. - 14 - - 0.5 - - - - 18 Max. 30.00 - 25 - 2 - -150 7 250 21.6 fF mW ppm ppm pF Unit MHz pF
Third overtone separation from 3*FNOM High side Third overtone separation from 3*FNOM Low side Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance
Table 4. Operating Conditions for FailSafe Commercial/Industrial Temperature Devices Parameter VDDC VDDA, VDDB TA CL CIN CXIN TPU 3.3V Supply Voltage 2.5V Supply Voltage Range 3.3V Supply Voltage Range Ambient Operating Temperature, Commercial Ambient Operating Temperature, Industrial Output Load Capacitance (Fout < 100 MHz) Output Load Capacitance (Fout > 100 MHz) Input Capacitance (except XIN) Crystal Input Capacitance (all internal caps off) 10 Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min. Max. Unit 3.135 3.465 2.375 2.625 3.135 3.465 0 -40 70 85 30 15 7 13 500 V V V C C pF pF pF pF ms
Note: 6. Ecliptek ECX-5788-13.500M, ECX-5807-19.440M, ECX-5872-19.53125M, ECX-5806-18.432M, ECX-5808-27.000M, ECX-5884-17.664M, ECX-5883-16.384M,ECX-5882-19.200M,ECX-5880-24.576M meet these specifications.
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CY23FS08
Table 5. Electrical Characteristics for FailSafe Commercial/Industrial Temperature Devices Parameter VIL VIH IIL IIH IOL IOH IDDQ Description Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current Output High Current Quiescent Current Test Conditions CMOS Levels, 30% of VDD CMOS Levels, 70% of VDD VIN = VSS (100k pull-up only) VIN = VDD (100k pull-down only) VOL = 0.5V, VDD = 2.5V VOL = 0.5V, VDD = 3.3V VOH = VDD - 0.5V, VDD = 2.5V VOH = VDD - 0.5V, VDD = 3.3V All Inputs grounded, PLL and DCXO in bypass mode, Reference Input = 0 18 20 18 20 250 0.7xVDD 50 50 Min. Typ. Max. 0.3xVDD Unit V V A A mA mA mA mA A
Table 6. Switching Characteristics for FailSafe Commercial/Industrial Temperature Devices Parameter[8] fREF fOUT fXIN tDC tSR(I) tSR(O) tSK(O) tSK(IB) tSK(PP) t()[7] tD()[7] tJ(CC) tLOCK Description Reference Frequency Output Frequency DCXO Frequency Duty Cycle Input Slew Rate Output Slew Rate Measured at VDD/2 Measured on REF1 Input, 30% to 70% of VDD Measured from 20% to 80% of VDD = 3.3V, 15 pF Load Measured from 20% to 80% of VDD =2.5V, 15 pF Load Output to Output Skew All outputs equally loaded, measured at VDD/2 Intrabank Skew Part to Part Skew Static Phase Offset Dynamic Phase Offset Cycle-to-Cycle Jitter Lock Time All outputs equally loaded, measured at VDD/2 Measured at VDD/2 Measured at VDD/2 Measured at VDD/2 Load = 15 pF, fOUT 6.25 MHz At room temperature with 18.432-MHz Crystal Industrial Grade 15-pF Load, Commercial Grade 15-pF Load, Industrial Grade Test Conditions Commercial Grade Min. 1.04 1.04 1.70 1.70 8.0 47 0.5 0.8 0.4 - - - - - - - - Typ. - - - - - - - - - 110 - - - 150 100 18 70 Max. 200 166.7 200 166.7 30 53 4.0 4.0 3.0 200 75 500 250 200 200 35 - Unit MHz MHz MHz MHz MHz % V/ns V/ns V/ns ps ps ps ps ps ps psRMS ms
Ordering Information
Part Number CY23FS08OI CY23FS08OIT CY23FS08OC CY23FS08OCT Lead-free CY23FS08OXI CY23FS08OXIT CY23FS08OXC CY23FS08OXCT 28-pin SSOP 28-pin SSOP - Tape and Reel 28-pin SSOP 28-pin SSOP - Tape and Reel Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C Package Type 28-pin SSOP 28-pin SSOP - Tape and Reel 28-pin SSOP 28-pin SSOP - Tape and Reel Product Flow Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C
Notes: 7. The t() reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as tSR(I) is maintained. 8. Parameters guaranteed by design and characterization, not 100% tested in production. 9. Includes typical board trace capacitance of 6-7pF each XIN, XOUT.
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CY23FS08
Package Drawing and Dimensions
28-Lead (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
FailSafe is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY23FS08
Document History Page
Document Title: CY23FS08 FailsafeTM 2.5V/ 3.3V Zero Delay Buffer Document #: 38-07518 Rev. *C REV. ** *A *B *C ECN NO. 123699 224067 276749 417645 Issue Date 04/23/03 See ECN See ECN See ECN Orig. of Change RGL RGL RGL New Data Sheet Removed (TLOCK) Lock Time Specification. Added Lead-free devices Added typical nos. on jitters Description of Change
RGL/ZJX Changed the XTAL Specifications table.
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